There has been disclosed a wafer for a semiconductor device where an impurity-containing oxide film, e.g., a tetra ethyl ortho silicate (TEOS) film, produced by a chemical vapor deposition (CVD) or the like; an electrically conductive film, e.g., a titanium nitride (TiN) film; a bottom anti-reflective coating (BARC) film; and a mask layer (photoresist film) are stacked in that order on a silicon substrate (see, e.g., Japanese Patent Application Publication No. 2006-190939 and corresponding US patent Application Publication No. 2006-141766 A1). The photoresist film is processed to have a predetermined pattern by photolithography and serves as a mask layer when the BARC film and the conductive film are etched.
As the scaling down of semiconductor devices has recently been in progress, it is needed to form a finer circuit pattern on a surface of the wafer described above. In order to form such a finer circuit pattern, it is required to form a small-sized opening (a via hole or a trench) on an etching target film by reducing a minimum feature dimension of the pattern of the photoresist film in the manufacturing process of a semiconductor device.
In order to form the small-sized pattern on the photoresist film, a highly transparent material may be employed to improve a pattern transfer fidelity by an exposure light. Since, however, such a highly transparent material has a low hardness, the strength of the mask layer is deteriorated, causing a pattern collapse. As a result, it becomes difficult to obtain a satisfactory etching resistance.
Such a trend is more strongly shown in a pattern having a line width of 10 nm or less and a high aspect ratio, for example. As such, a formation of a finer pattern and an etching resistance are in a trade-off (antinomy) relationship in the mask layer, e.g., the photoresist film.
In the meantime, there has been disclosed a technique for forming a fine line width of a line portion of a mask layer in the manufacturing process of a semiconductor device (see, e.g., Japanese Patent Application Publication No. 2004-134553)
In this Japanese Patent Application Publication, a resist pattern forming method has been disclosed. Specifically, a resist film is formed on a base layer of a wafer by employing a resist material that can be contracted by the irradiation of an electron beam and, then, a resist pattern having a specific line width is formed by subjecting the resist film to an exposure treatment. Thereafter, by irradiating an electron beam, the line width of the resist pattern is reduced.
Although the scaling-down (hereinafter, referred to as “trimming”) of the line width of the resist pattern can be accomplished by the aforementioned technique, the trimmed resist pattern is not reinforced, causing a pattern collapse. Accordingly, it is difficult to form in a processing target layer a small-sized opening that meets the demand for the scaling-down of a semiconductor device.